Davicom DM9012DEP 10/100Mbps Fast Ethernet MAC Chip único Fast Ethernet NIC Controller

MII, PCI Interface, PHY

SMT

PHY, MAC

Davicom

DM9012DEP

Taiwan, China

Network Interface Adapter, Surveillance Camera, Embedded System, Ethernet Hub, Ethernet Switch

DM9012D seriers

The DM9102D is a fully integrated and cost effective singlechip Fast Ethernet NIC controller. It is designed with lowpower and high performance process. It is a 2.5/3.3V devicewith 5V tolerance.The DM9102D provides direct interface to the PCI bus andsupports bus master mode to achieve the high performanceof the PCI bus. It fully complies with PCI 2.2. In the mediaside, the DM9102D interfaces to the UTP3, 4, 5 in 10Base-Tand the UTP5 in 100Base-TX. It is fully compliant with theIEEE 802.3u Spec. The auto-negotiation andHP Auto-MDIX function can automatically configure theDM9102D to take the maximum advantage of its abilities.The DM9102D also supports IEEE 802.3x's full-duplex flowcontrol to prevent the receive overflow of link partner. TheIPv4 IP/TCP/UDP checksum generation and checking canreduce the system CPU utilization.The DM9102D supports two types of power managementmechanisms. The main mechanism is based on the OnNowarchitecture, which is required for PC99. The alternativemechanism is based upon the remote Wake-On-LANmechanism.

128-pin LQFP

Integrated Fast Ethernet MAC, Physical Layer, and transceiver in one chip, 128-pin LQFP with CMOS process, +2.5/3.3V Power supply with +5V tolerant I/O, Complies with PCI specification 2.2, PCI bus master architecture, PCI bus burst mode data transfer, Two large independent transmission and receipt FIFO, Up to 256K bytes Boot EPROM or Flash interface, EEPROM 93C46 interface automatically supports node ID load and configuration information, Complies with IEEE 802.3u 100Base-TX and 802.3 10Base-T, Complies with IEEE 802.3u auto-negotiation protocol for automatic link type selection, Supports IEEE 802.3x Full Duplex Flow Control, VLAN frame length support, IP/TCP/UDP checksum generation and checking, Zero copy supporting, Complies with ACPI and PCI Bus Power Management, Supports the MII (Media Independent Interface) for an external PHY, Supports Wake-On-LAN function and remote wake-up (Magic packet, Link Change, and Microsoft wake-up frame), Supports 4 Wake-On-LAN (WOL) signals (active high pulse, active low pulse, active high, active low), High-performance 100Mbps clock generator and data recovery circuit, Digital clock recovery circuit using advanced digital algorithm to reduce jitter, Adaptive equalization circuit and Baseline wandering restoration circuit for 100Mbps receiver, Provides Loopback mode for easy system diagnostics, Supports HP Auto-MDIX, Low power consumption modes: Power reduced mode (cable detection), Power down mode, Selectable TX drivers for 1:1 or 1.25:1 transformers for additional power reduction (1.25:1 transformers for Non Auto-MDIX only).

-40~ + 85

10/100Mbps

128-pin LQFP

3.3V, I/O 3.3V to 5V

IEEE 802.3u, IEEE 802.3x

Multiple of 90

40X20X12 cm